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document number: MC33912 rev. 4.0, 2/2008 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. lin system basis chip with dc motor pre-driver and current sense the 33912 is a serial peripheral interface (spi) -controlled system basis chip (sbc), combining many frequently used functions in an mcu-based system, plus a loca l interconnect network (lin) transceiver. the 33912 has a 5.0v - 60ma low dropout regulator with full protection and reporting feat ures. the device provides full spi- readable diagnostics and a selectable timing watchdog for detecting errant operation. the lin protocol specification 2.0 compliant lin transceiver has waveshaping circuitry that can be disabled for higher data rates. two 60ma high side switches and two 160ma low side switches with output protection are available for driving resistive and inductive loads. all outputs can be pulse-width modulated (pwm). four high voltage inputs are available for use in contact monitoring, or as external wake-up inputs. these inputs can be used as high voltage analog inputs. the voltage on these pins is divided by a selectable ratio and available via an analog multiplexer. the 33912 has three main operating modes: normal (all functions available), sleep (v dd off, wake-up via lin, wake-up inputs (l1-l4), cyclic sense and forced wake-up), and stop (v dd on with limited current capability, wake-up via cs , lin bus, wake-up inputs, cyclic sense, forced wake-up and external reset). the 33912 is compatible with li n protocol specification 2.0. features ? full-duplex spi interface at frequencies up to 4mhz ? lin transceiver capable of up to 100kbps with wave shaping ? two 60ma high side and two 160 ma low side protected switches ? four high voltage analog/logic inputs ? configurable window watchdog ? 5.0v low drop regulator with fault detection and low voltage reset (lvr) circuitry ? current sense module ? switched/protected 5.0v output (used for hall sensors) ? pb-free packaging designated by suffix code ac figure 1. 33912 simplified application diagram 33912 ordering information device temperature range (t a ) package MC33912bac/r2 - 40c to 125c 32-lqfp mc34912bac/r2 -40c to 85c ac suffix (pb-free) 98ash70029a 32-pin lqfp system basis chip with lin 2 nd generation m mcu 33912 lin interface vs1 vs2 vsense hs1 l1 l2 l3 l4 ls1 ls2 isenseh isensel hvdd hs2 wdconf agnd lgnd pgnd lin vdd pwmin adout0 adout1 mosi miso sclk cs rxd txd irq rst v bat
analog integrated circuit device data 2 freescale semiconductor 33912 internal block diagram internal block diagram figure 2. 33912 simplifi ed internal block diagram voltage regulator high side control module interrupt control module lvi, hvi, hti, oci reset control module lvr, hvr, htr, wd window watchdog module spi & control lin physical layer wake-up module digital input module analog input chip temperature sense module analog multiplexer module agnd pgnd hs1 l1 lin rst irq vs2 vs1 vdd pwmin miso mosi sclk cs adout0 rxd txd lgnd wdconf vs2 low side control module l2 5v output module hvdd hs2 vs2 v bat sense module vsense ls2 ls1 current sense module l3 l4 isensel isenseh adout1 internal bus
analog integrated circuit device data freescale semiconductor 3 33912 pin connections pin connections figure 3. 33912 pin connections table 1. 33912 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 21 . pin pin name formal name definition 1 rxd receiver output this pin is the receiver output of the lin interface which reports the state of the bus voltage to the mcu interface. 2 txd transmitter input this pin is the transmitter input of the lin interface which controls the state of the bus output. 3 miso spi output spi (serial peripheral interface) data output. when cs is high, pin is in the high-impedance state. 4 mosi spi input spi (serial peripheral interface) data input. 5 sclk spi clock spi (serial peripheral interface) clock input. 6 cs spi chip select spi (serial peripheral interface) chip select input pin. cs is active low. 7 adout0 analog output pin 0 analog multiplexer output. 8 pwmin pwm input high side and low side pulse width modulation input. 9 rst internal reset i/o bidirectional reset i/o pin - driven lo w when any internal reset source is asserted. rst is active low. 10 irq internal interrupt output interrupt output pin, indicating wake-up events from stop mode or events from normal and normal request modes. irq is active low. 11 adout1 analog output pin 1 current sense analog output. 8 pwmin 7 adout0 5 sclk 4 mosi 3 miso 1 rxd 2 txd 6 cs 17 ls2 18 pgnd 20 l4 21 l3 22 l2 24 hs2 23 l1 19 ls1 25 hs1 26 vs2 28 nc 29 vsense 30 hvdd 32 agnd 31 vdd 27 vs1 16 isenseh 15 13 lin 12 wdconf 11 adout1 9 rst 10 irq 14 isensel lgnd
analog integrated circuit device data 4 freescale semiconductor 33912 pin connections 12 wdconf watchdog configuration pin this input pin is for configuration of the watchdog period and allows the disabling of the watchdog. 13 lin lin bus this pin represents the single-wire bus transmitter and receiver. 14 lgnd lin ground pin this pin is the device lin ground connecti on. it is internally connected to the pgnd pin. 15 16 isensel isenseh current sense pins current sense differential inputs. 17 19 ls2 ls1 low side outputs relay drivers low side outputs. 18 pgnd power ground pin this pin is the device low side ground co nnection. it is internally connected to the lgnd pin. 20 21 22 23 l4 l3 l2 l1 wake-up inputs these pins are the wake -up capable digital inputs (1) . in addition, all lx inputs can be sensed analog via the analog multiplexer. 24 25 hs2 hs1 high side outputs high side switch outputs. 26 27 vs2 vs1 power supply pin these pins are device battery level power supply pins.vs2 is supplying the hsx drivers while vs1 suppl ies the remaining blocks. (2) 29 vsense voltage sense pin battery voltage sense input. (3) 30 hvdd hall sensor supply output +5.0v switchable supply output pin. (4) 31 vdd voltage regulator output +5.0v main voltage regulator output pin. (5) 32 agnd analog ground pin this pin is the device analog ground connection. notes 1. when used as digital input, a series 33k ? resistor must be used to prot ect against automotive transients. 2. reverse battery protection series diodes must be us ed externally to protect the internal circuitry. 3. this pin can be connected directly to the battery line for vo ltage measurements. the pin is self protected against reverse ba ttery connections. it is strongly recommended to connect a 10k ? resistor in series with this pin for protection purposes. 4. external capacitor (1f < c < 10f; 0.1 ? < esr < 5 ? ) required. 5. external capacitor (2f < c < 100f; 0.1 ? < esr < 10 ? ) required. table 1. 33912 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 21 . pin pin name formal name definition
analog integrated circuit device data freescale semiconductor 5 33912 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings supply voltage at vs1 and vs2 normal operation (dc) transient conditions (load dump) v sup(ss) v sup(pk) -0.3 to 27 -0.3 to 40 v supply voltage at vdd v dd -0.3 to 5.5 v input / output pins voltage (6) cs , rst , sclk, pwmin, adout0, adout1, mosi, miso, txd, rxd, hvdd interrupt pin (irq ) (7) v in v in(irq) -0.3 to v dd +0.3 -0.3 to 11 v hs1 and hs2 pin voltage (dc) v hs - 0.3 to v sup +0.3 v ls1 and ls2 pin voltage (dc) v ls -0.3 to 45 v l1, l2, l3 and l4 pin voltage normal operation with a series 33k resistor (dc) transient input voltage with external component (according to iso7637-2) (see figure 5 , page 17 ) v lxdc v lxtr -18 to 40 100 v isenseh and isensel pin voltage (dc) v isense -0.3 to 40 v vsense pin voltage (dc) v vsense -27 to 40 v lin pin voltage normal operation (dc) transient input voltage with external component (according to iso7637-2) (see figure 4 , page 17 ) v busdc v bustr -18 to 40 -150 to 100 v vdd output current i vdd internally limited a esd voltage (8) human body model - lin pin human body model - all other pins machine model charge device model corner pins (pins 1, 8, 9, 16, 17, 24, 25 and 32) all other pins (pins 2-7, 10-15, 18-23, 26-31) v esd1-1 v esd1-2 v esd2 v esd3-1 v esd3-2 8000 2000 200 750 500 v notes 6. exceeding voltage limits on spec ified pins may cause a malfunction or permanent damage to the device. 7. extended voltage range for programming purpose only. 8. testing is performed in accordanc e with the human body model (c zap = 100pf, r zap = 1500 ?), machine model (c zap = 200pf, r zap = 0 ?) and the charge device model, robotic (c zap = 4.0pf ).
analog integrated circuit device data 6 freescale semiconductor 33912 electrical characteristics maximum ratings thermal ratings operating ambient temperature (9) 33912 34912 t a -40 to 125 -40 to 85 c operating junction temperature t j -40 to 150 c storage temperature t stg -55 to 150 c thermal resistance, junction to ambient natural convection, single layer board (1s) (10) , (11) natural convection, four layer board (2s2p) (10) , (12) r ja 85 56 c/w thermal resistance, junction to case (13) r jc 23 c/w peak package reflow temperature during reflow (14) , (15) t pprt note 15 c notes 9. the limiting factor is junction temperatur e; taking into account the power dissipat ion, thermal resistance, and heat sinking. 10. junction temperature is a function of on-chip power dissipat ion, package thermal resistance, mounting site (board) temperatu re, ambient temperature, air flow, power dissipation of othe r components on the board, and board thermal resistance. 11. per jedec jesd51-2 with the singl e layer board (jesd51-3) horizontal. 12. per jedec jesd51-6 with the board (jesd51-7) horizontal. 13. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1 ). 14. pin soldering temperature limit is for 10 seconds maximum du ration. not designed for immersion soldering. exceeding these li mits may cause malfunction or permanent damage to the device. 15. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. table 2. maximum ratings (continued) all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data freescale semiconductor 7 33912 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33912 and -40c t a 85c for the 34912, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit supply voltage range (vs1, vs2) nominal operating voltage v sup 5.5 ? 18 v functional operating voltage (16) v supop ? ? 27 v load dump v supld ? ? 40 v supply current range ( v sup = 13.5v) normal mode (i out at v dd = 10ma), lin recessive state (17) i run ? 4.5 10 ma stop mode, vdd on with i out = 100a, lin recessive state (17) , (18) , (19) 5.5v < v sup < 12v v sup = 13.5v i stop ? ? 48 58 80 90 a sleep mode, vdd off, lin recessive state (17) , (19) 5.5v < v sup < 12v 12v v sup < 13.5v i sleep ? ? 27 37 35 48 a cyclic sense supply current adder (20) i cyclic ? 10 ? a supply under/over voltage detections power-on reset (batfail) (21) threshold (measured on vs1) (20) hysteresis (measured on vs1) (20) v batfail v batfail_hys 1.5 ? 3.0 0.9 3.9 ? v vsup under voltage detection (vsuv flag) (normal and normal request modes, interrupt generated) threshold (measured on vs1) hysteresis (measured on vs1) v suv v suv_hys 5.55 ? 6.0 1.0 6.6 ? v vsup over voltage detection (vso v flag) (normal and normal request modes, interrupt generated) threshold (measured on vs1) hysteresis (measured on vs1) v sov v sov_hys 18 ? 19.25 1.0 20.5 ? v notes 16. device is fully functional . all features are operating. 17. total current (i vs1 + i vs2 ) measured at gnd pins excluding all loads, cyclic sense disabled. 18. total i dd current (including loads) below 100a. 19. stop and sleep modes current will increase if v sup exceeds13.5v. 20. this parameter is guaranteed by proc ess monitoring but not production tested. 21. the flag is set during power up sequence. to clear the flag, a spi read must be performed.
analog integrated circuit device data 8 freescale semiconductor 33912 electrical characteristics static electrical characteristics voltage regulator (22) (vdd) normal mode output voltage 1.0ma < i vdd < 50ma; 5.5v < v sup < 27v v ddrun 4.75 5.00 5.25 v normal mode output current limitation i vddrun 60 110 200 ma dropout voltage (23) i vdd = 50ma v dddrop ? 0.1 0.25 v stop mode output voltage i vdd < 5ma v ddstop 4.75 5.0 5.25 v stop mode output current limitation i vddstop 6.0 12 36 ma line regulation normal mode, 5.5v < v sup < 18v; i vdd = 10ma stop mode, 5.5v < v sup < 18v; i vdd = 1.0ma lr run lr stop ? ? 20 5.0 25 25 mv load regulation normal mode, 1.0ma < i vdd < 50ma stop mode, 0.1ma < i vdd < 5ma ld run ld stop ? ? 15 10 80 50 mv over-temperature prewarning (junction) (24) interrupt generated, vddot bit set t pre 110 125 140 c over-temperature prewarning hysteresis (24) t pre_hys ? 10 ? c over-temperature shutdown temperature (junction) (24) t sd 155 170 185 c over-temperature shutdown hysteresis (24) t sd_hys ? 10 ? c hall sensor supply output (25) (hvdd) v dd voltage matching h vddacc = (hvdd-vdd) / vdd * 100% i hvdd = 15ma h vddacc -2.0 ? 2.0 % current limitation i hvdd 20 30 50 ma dropout voltage i hvdd = 15ma; i vdd = 5ma h vdddrop ? 160 300 mv line regulation i hvdd = 5ma; i vdd = 5ma lr hvdd ? 25 40 mv load regulation 1ma > i hvdd > 15ma; i vdd = 5ma ld hvdd ? 10 20 mv notes 22. specification with external capacitor 2f < c < 100f and 100m ? esr 10 ?. 23. measured when voltage has dropped 250mv below its nominal value (5v). 24. this parameter is guaranteed by pr ocess monitoring but not production tested. 25. specification with external capacitor 1f < c < 10f and 100m ? esr 10 ?. table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33912 and -40c t a 85c for the 34912, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 33912 electrical characteristics static electrical characteristics rst input/output pin (rst ) vdd low voltage reset threshold v rst th 4.3 4.5 4.7 v low-state output voltage i out = 1.5ma; 3.5v v sup 27v v ol 0.0 ? 0.9 v high-state output current (0 < v out < 3.5v) i oh -150 -250 -350 a pull-down current limitation (internally limited) v out = v dd i pd_max 1.5 ? 8.0 ma low-state input voltage v il -0.3 ? 0.3 x v dd v high-state input voltage v ih 0.7 x v dd ? v dd +0.3 v miso spi output pin (miso) low-state output voltage i out = 1.5ma v ol 0.0 ? 1.0 v high-state output voltage i out = -250a v oh v dd -0.9 ? v dd v tri-state leakage current 0v v miso v dd i trimiso -10 ? 10 a spi input pins (mosi, sclk, cs ) low-state input voltage v il -0.3 ? 0.3 x v dd v high-state input voltage v ih 0.7 x v dd ? v dd +0.3 v mosi, sclk input current 0v v in v dd i in -10 ? 10 a cs pull-up current 0v < v in < 3.5v i pucs 10 20 30 a interrupt output pin ( irq ) low-state output voltage i out = 1.5ma v ol 0.0 ? 0.8 v high-state output voltage i out = -250a v oh v dd -0.8 ? v dd v leakage current v dd v out 10 v v oh ? ? 2.0 ma pulse width modulation input pin (pwmin) low-state input voltage v il -0.3 ? 0.3 x v dd v high-state input voltage v ih 0.7 x v dd ? v dd +0.3 v pull-up current 0v < v in < 3.5v i pupwmin 10 20 30 a table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33912 and -40c t a 85c for the 34912, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33912 electrical characteristics static electrical characteristics high side outputs hs1 and hs2 pins (hs1, hs2) output drain-to-source on resistance t j = 25c, i load = 50ma; v sup > 9.0v t j = 150c, i load = 50ma; v sup > 9.0v (26) t j = 150c, i load = 30ma; 5.5v < v sup < 9.0v (26) r ds(on) ? ? ? ? ? ? 7.0 10 14 ? output current limitation (27) 0v < v out < v sup - 2.0v i limhsx 60 120 250 ma open load current detection (28) i olhsx ? 5.0 7.5 ma leakage current -0.2v < v hsx < v s2 + 0.2v i leak ? ? 10 a short-circuit detection threshold (29) 5.5v < v sup < 27v v thsc v sup -2.0 ? ? v over-temperature shutdown (30) , (35) t hssd 150 165 180 c over-temperature shutdown hysteresis (35) t hssd_hys ? 10 ? c low side outputs ls1 and ls2 pins (ls1, ls2) output drain-to-source on resistance t j = 25c, i load = 150ma, v sup > 9.0v t j = 125c, i load = 150ma, v sup > 9.0v t j = 125c, i load = 120ma, 5.5v < v sup < 9.0v r ds(on) ? ? ? ? ? ? 2.5 4.5 10 ? output current limitation (31) 2.0v < v out < v sup i limlsx 160 275 350 ma open load current detection (32) i ollsx ? 8.0 12 ma leakage current -0.2v < v out < vs1 i leak ? ? 10 a active output energy clamp i out = 150ma v clamp v sup +2.0 ? v sup +5.0 v short-circuit detection threshold (33) 5.5v < v sup < 27v v thsc 2.0 ? ? v over-temperature shutdown (34) , (35) t lssd 150 165 180 c over-temperature shutdown hysteresis (35) t lssd_hys ? 10 ? c notes 26. this parameter is production tested up to t a = 125c and guaranteed by process monitoring up to t j = 150c.. 27. when over-current occurs, the corresponding high side stays on with limited current capability and the hsxcl flag is set in the hssr . 28. when open load occurs, the flag (hsxop) is set in the hssr . 29. when short-circuit occurs and if hvse fl ag is enabled, both hs automatic shutdown. 30. when over-temperature shutdown occurs, both high si des are turned off. all flags in hssr are set. 31. when over-current occurs, the corresponding low side stays on with limited current capability and the lsxcl flag is set in t he lssr . 32. when open load occurs, the flag (lsxop) is set in the lssr. 33. when short-circuit occurs and if hvse flag is enabled, both ls automatic shutdown 34. when over-temperature shutdown occurs, both low si des are turned off. all flags in lssr are set. 35. guaranteed by characterization but not production tested table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33912 and -40c t a 85c for the 34912, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33912 electrical characteristics static electrical characteristics l1, l2, l3 and l4 input pins (l1, l2, l3, l4) low detection threshold 5.5v < v sup < 27v v thl 2.0 2.5 3.0 v high detection threshold 5.5v < v sup < 27v v thh 3.0 3.5 4.0 v hysteresis 5.5v < v sup < 27v v hys 0.5 1.0 1.5 v input current (36) -0.2v < v in < vs1 i in -10 ? 10 a analog input impedance (37) r lxin 800 1550 ? k ? analog input divider ratio (ratio lx = v lx / v adout0 ) lxds (lx divider select) = 0 lxds (lx divider select) = 1 ratio lx 0.95 3.42 1.0 3.6 1.05 3.78 analog output offset ratio lxds (lx divider select) = 0 lxds (lx divider select) = 1 v ratiolx- offset -80 -22 0.0 0.0 80 22 mv analog inputs matching lxds (lx divider select) = 0 lxds (lx divider select) = 1 lx matching 96 96 100 100 104 104 % window watchdog configuration pin (wdconf) external resistor range r ext 20 ? 200 k ? watchdog period accuracy with extern al resistor (excluding resistor accuracy) (38) wd acc -15 ? 15 % analog multiplexer internal chip temperature sense gain s ttov ? 10.5 ? mv/k vsense input divider ratio (ratio vsense = v vsense / v adout0 ) 5.5v < v sup < 27v ratio vsense 5.0 5.25 5.5 vsense output related offset -40c < t a < -20c offset vsense -30 -45 ? ? 30 45 mv analog outputs (adout0 and adout1) maximum output voltage -5ma < i o < 5ma v out_max v dd -0.35 ? v dd v minimum output voltage -5ma < i o < 5ma v out_min 0.0 ? 0.35 v notes 36. analog multiplexer input di sconnected from lx input pin. 37. analog multiplexer input connected to lx input pin. 38. watchdog timing period ca lculation formula: t pwd [ms] = 0.466 * (r ext - 20) + 10 (r ext in k ?) table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33912 and -40c t a 85c for the 34912, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33912 electrical characteristics static electrical characteristics current sense amplif ier (isenseh, isensel) gain csgs (current sense gain select) = 0 csgs (current sense gain select) = 1 g 29 14 30 14.5 31 15 differential input impedance csgs (current sense gain select) = 0 csgs (current sense gain select) = 1 diff 2.0 5.0 10 20 30 50 k ? common mode input impedance csgs (current sense gain select) = 0 csgs (current sense gain select) = 1 cm 75 75 ? ? 300 300 k ? isenseh, isensel input voltage range v in -0.2 ? 3.0 v input offset voltage csaz (current sense auto zero) = 0 csaz (current sense auto zero) = 1 v in_offset -15 -2.0 ? ? 15 2.0 mv rxd output pin (lin physical layer) (rxd) low-state output voltage i out = 1.5ma v ol 0.0 ? 0.8 v high-state output voltage i out = -250a v oh v dd -0.8 ? v dd v txd input pin (lin physical layer) (txd) low-state input voltage v il -0.3 ? 0.3 x v dd v high-state input voltage v ih 0.7 x v dd ? v dd +0.3 v pin pull-up current, 0v < v in < 3.5v i puin 10 20 30 a table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33912 and -40c t a 85c for the 34912, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 33912 electrical characteristics static electrical characteristics lin physical layer, transceiver (lin) (39) output current limitation dominant state, v bus = 18v i buslim 40 120 200 ma leakage output current to gnd dominant state; v bus = 0v; v bat = 12v recessive state; 8v < v bat < 18v; 8v < v bus < 18v; v bus v bat gnd disconnected; gnd device = v sup ; v bat = 12v; 0 < v bus < 18v v bat disconnected; v sup_device = gnd; 0 < v bus < 18v i bus_pas_dom i bus_pas_rec i bus_no_gnd i bus -1.0 ? -1.0 ? ? ? ? ? ? 20 1.0 100 ma a ma a receiver input voltages receiver dominant state receiver recessive state receiver threshold center (v th_dom + v th_rec )/2 receiver threshold hysteresis (v th_rec - v th_dom ) v busdom v busrec v bus_cnt v hys ? 0.6 0.475 ? ? ? 0.5 ? 0.4 ? 0.525 0.175 v sup lin transceiver output voltage recessive state, txd high, i out = 1.0a dominant state, txd low, 500 ? external pull-up resistor, ldvs = 0 dominant state, txd low, 500 ? external pull-up resistor, ldvs = 1 v lin_rec v lin_dom_0 v lin_dom_1 v sup -1.0 ? ? ? 1.1 1.7 ? 1.4 2 v lin pull-up resistor to v sup r slave 20 30 60 k ? over-temperature shutdown (40) t linsd 150 165 180 c over-temperature shutdown hysteresis t linsd_hys ? 10 ? c notes 39. parameters guaranteed for 7.0v v sup 18v. 40. when over-temperature shutdown occurs, the lin bus goes in recessive state and the flag linot in linsr is set. table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33912 and -40c t a 85c for the 34912, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor 33912 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33912 and -40c t a 85c for the 34912, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit spi interface timing (see figure 13 , page 20 ) spi operating frequency f spiop ??4.0mhz sclk clock period t ps clk 250 ? n/a ns sclk clock high time (41) t w sclkh 110 ? n/a ns sclk clock low time (41) t w sclkl 110 ? n/a ns falling edge of cs to rising edge of sclk (41) t lead 100 ? n/a ns falling edge of sclk to cs rising edge (41) t lag 100 ? n/a ns mosi to falling edge of sclk (41) t sisu 40 ? n/a ns falling edge of sclk to mosi (41) t sih 40 ? n/a ns miso rise time (41) c l = 220pf t rso ? 40 ? ns miso fall time (41) c l = 220pf t fso ? 40 ? ns time from falling or rising edges of cs to: (41) - miso low-impedance - miso high-impedance t soen t sodis 0.0 0.0 ? ? 50 50 ns time from rising edge of sclk to miso data valid (41) 0.2 x v dd miso 0.8 x v dd , c l = 100pf t valid 0.0 ? 75 ns rst output pin reset low-level duration after v dd high (see figure 12 , page 20 ) t rst 0.65 1.0 1.35 ms reset deglitch filter time t rstdf 350 600 900 ns window watchdog configuration pin (wdconf) watchdog time period (42) external resistor r ext = 20k ? (1%) external resistor r ext = 200k ? (1%) without external resistor r ext (wdconf pin open) t pwd 8.5 79 110 10 94 150 11.5 108 205 ms current sense amplifier (41) common mode rejection ratio cmr 70 ? ? db supply voltage rejection ratio (43) svr 60 ? ? db gain bandwidth product gbp 0.75 3.0 ? mhz output slew-rate sr 0.5 ? ? v/s notes 41. this parameter is guaranteed by pr ocess monitoring but not production tested. 42. watchdog timing period ca lculation formula: t pwd [ms] = 0.466 * (r ext - 20) + 10 (r ext in k ?) 43. analog outputs are supplied by v dd
analog integrated circuit device data freescale semiconductor 15 33912 electrical characteristics dynamic electrical characteristics l1, l2, l3 and l4 inputs wake-up filter time t wuf 8.0 20 38 s state machine timing delay between cs low-to-high transition (at end of spi stop command) and stop mode activation (44) t stop ? ? 5.0 s normal request mode timeout (see figure 12 , page 20 ) t nr tout 110 150 205 ms delay between spi command and hs /ls turn on (45) 9v < v sup < 27v t s- on ? ? 10 s delay between spi command and hs /ls turn off (45) 9v < v sup < 27v t s- off ? ? 10 s delay between normal request and normal mode after a watchdog trigger command (normal request mode) (44) t snr2n ? ? 10 s delay between cs wake-up ( cs low to high) in stop mode and: normal request mode, vdd on and rst high first accepted spi command t wucs t wuspi 9.0 90 15 ? 80 n/a s minimum time between rising and falling edge on the cs t 2 cs 4.0 ? ? s lin physical layer: driver characteristics for normal slew rate - 20.0kbit/sec (46) , (47) duty cycle 1: d1 = t bus_rec(min) /(2 x t bit ), t bit = 50s 7.0v v sup 18v d1 0.396 ? ? duty cycle 2: d2 = t bus_rec(max) /(2 x t bit ), t bit = 50s 7.6v v sup 18v d2 ? ? 0.581 lin physical layer: driver characteristics for slow slew rate - 10.4kbit/sec (46) , (48) duty cycle 3: d3 = t bus_rec(min) /(2 x t bit ), t bit = 96s 7.0v v sup 18v d3 0.417 ? ? s duty cycle 4: d4 = t bus_rec(max) /(2 x t bit ), t bit = 96s 7.6v v sup 18v d4 ? ? 0.590 s notes 44. this parameter is guaranteed by pr ocess monitoring but not production tested. 45. delay between turn on or off command (rising edge on cs ) and hs or ls on or off, excluding rise or fall time due to external load. 46. bus load r bus and c bus 1.0nf / 1.0 k ? , 6.8 nf / 660 ? , 10nf / 500 ? . measurement thresholds: 50% of txd signal to lin signal threshold defined at each parameter. see figure 6 , page 18 . 47. see figure 7 , page 18 . 48. see figure 8 , page 18 . table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33912 and -40c t a 85c for the 34912, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 33912 electrical characteristics dynamic electrical characteristics lin physical layer: driver characteristics for fast slew rate lin fast slew rate (programming mode) sr fast ?20?v / s lin physical layer: characteristics and wake-up timings (49) propagation delay and symmetry (50) propagation delay receiver, t rec_pd =max (t rec_pdr , t rec_pdf ) symmetry of receiver propagation delay t rec_pdf - t rec_pdr t rec_pd t rec_sym ? - 2.0 3.0 ? 6.0 2.0 s bus wake-up deglitcher (sleep and stop modes) (51) t propwl 42 70 95 s bus wake-up event reported from sleep mode (52) from stop mode (53) t wake t wake ? 9.0 ? 13 1500 17 s txd permanent dominant state delay t txddom 0.65 1.0 1.35 s pulse width modulation input pin (pwmin) pwmin pin (54) max. frequency to drive hs and ls output pins f pwmin 10 khz notes 49. v sup from 7.0v to 18v, bus load r bus and c bus 1.0nf / 1.0k ? , 6.8nf / 660 ? , 10nf / 500 ? . measurement thresholds: 50% of txd signal to lin signal threshold defined at each parameter. see figure 6 , page 18 . 50. see figure 9 , page 19 51. see figure 10 , page 19 for sleep and figure 11 , page 19 for stop mode. 52. the measurement is done with 1 f capacitor and 0ma current load on v dd . the value takes into account the delay to charge the capacitor. the delay is measured between the bus wake-up threshold (v buswu ) rising edge of the lin bus and when v dd reaches 3.0v. see figure 10 , page 19 . the delay depends of the load and capacitor on v dd . 53. in stop mode, the delay is measured between the bus wake-up threshold (v buswu ) and the falling edge of the irq pin. see figure 11 , page 19 . 54. this parameter is guaranteed by pr ocess monitoring but not production tested. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33912 and -40c t a 85c for the 34912, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 17 33912 electrical characteristics timing diagrams timing diagrams figure 4. test circuit for transient test pulses (lin) figure 5. test circuit for transient test pulses (lx) figure 6. test circuit for lin timing measurements note waveform per iso 7637-2. test pulses 1, 2, 3a, 3b. lin transient pulse pgnd generator 1.0nf ( note ) gnd 33912 lgnd agnd l1, l2, l3, l4 transient pulse pgnd generator 1.0 nf (note) 10 k ? note waveform per iso 7637-2. test pulses 1, 2, 3a, 3b,. gnd 33912 lgnd agnd r0 and c0 combinations: ? 1.0k ? and 1.0nf ? 660 ? and 6.8nf ? 500 ? and 10nf v sup txd rxd lin r0 c0 c0
analog integrated circuit device data 18 freescale semiconductor 33912 electrical characteristics timing diagrams figure 7. lin timing meas urements for normal slew rate figure 8. lin timing measurements for slow slew rate txd lin rxd t bit t bit t bus_dom (max) t bus_rec (min) t rec - max t dom - min t dom - min t rrec t rdom 28.4% v sup 58.1% v sup 40.0% v sup 60.0% v sup 74.4% v sup 42.2% v sup 40.0% v sup 58.1% v sup 28.4% v sup t bus_dom (min) t bus_rec (max) t dom - max t rec - min v lin_rec txd lin rxd t bit t bit t bus_dom (max) t bus_rec (min) t rec - max t dom - min t dom - min t rrec t rdom 25.1% v sup 61.6% v sup 40.0% v sup 60.0% v sup 77.8% v sup 38.9% v sup 40.0% v sup 61.6% v sup 25.1% v sup t bus_dom (min) t bus_rec (max) t dom - max t rec - min v lin_rec
analog integrated circuit device data freescale semiconductor 19 33912 electrical characteristics timing diagrams figure 9. lin receiver timing figure 10. lin wake-up sleep mode timing figure 11. lin wake-up stop mode timing v busrec v busdom v sup lin bus signal t rx_pdr t rx_pdf rxd v lin_rec dominant level 0.4 v sup v lin_rec lin vdd t prop wl t wake irq lin vrec tpropwl twake dominant level 0.4vsup dominant level 0.4 v sup v lin_rec t propwl t wake
analog integrated circuit device data 20 freescale semiconductor 33912 electrical characteristics timing diagrams figure 12. power on reset and normal request timeout timing figure 13. spi timing characteristics v sup v dd rst t rst t nrtout d0 d0 undefined don?t care d7 don?t care t lead t sih t sisu t lag t psclk t wsclkh t wsclkl t valid don?t care d7 t sodis cs sclk mosi miso t soen
analog integrated circuit device data freescale semiconductor 21 33912 functional description introduction functional description introduction the 33912 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. for automotive body electronics, the 33912 is well suited to perform relay control in applications like window lift, sunroof, etc. via lin bus. power switches are provided on the device configured as high side and low side outputs. other ports are also provided, which include a current and voltage sense port, a hall sensor port supply, and four wake-up capable pins. an internal voltage regulator provides power to a mcu device. also included in this device is a lin physical layer, which communicates using a single wire. this enables this device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and one for ground. functional pin description see figure 1, 33912 simplified application diagram , page 1 , for a graphic representation of the various pins referred to in the following paragraphs. also, see the pin diagram on page 3 for a description of the pin locations in the package. receiver output pin (rxd) the rxd pin is a digital output. it is the receiver output of the lin interface and reports the state of the bus voltage: rxd low when lin bus is dominant, rxd high when lin bus is recessive. transmitter input pin (txd) the txd pin is a digital input. it is the transmitter input of the lin interface and controls the state of the bus output (dominant when txd is low, recessive when txd is high). this pin has an internal pull-up to force recessive state in case the input is left floating. lin bus pin (lin) the lin pin represents the single-wire bus transmitter and receiver. it is suited for automotive bus systems and is compliant to the lin bus specification 2.0. the lin interface is only active during normal and normal request modes. serial data clock pin (sclk) the sclk pin is the spi clock input pin. miso data changes on the negative transi tion of the sclk. mosi is sampled on the positive edge of the sclk. master out slave in pin (mosi) the mosi digital pin receives spi data from the mcu. this data input is sampled on the positive edge of sclk. master in slave out pin (miso) the miso pin sends data to an spi-enabled mcu. it is a digital tri-state output used to shift serial data to the microcontroller. data on th is output pin changes on the negative edge of the sclk. when cs is high, this pin will remain in high-impedance state. chip select pin (cs ) cs is an active low digital input. it must remain low during a valid spi communication and allow for several devices to be connected in the same spi bus without contention. a rising edge on cs signals the end of the transmission and the moment the data shifted in is latched. a valid transmission must consist of 8 bits only. while in stop mode, a low-to-high level transition on this pin will generate a wake-up condition for the 33912. analog multiplexer pin (adout0) the adout0 pin can be configured via the spi to allow the mcu a/d converter to re ad the several inputs of the analog multiplexer, includi ng the vsense, l1, l2, l3, l4 input voltages, and the internal junction temperature. current sense amplifier pin (adout1) the adout1 pin is an analog interface to the mcu a/d converter. it allows the mcu to read the output of the current sense amplifier. pwm input control pin (pwmin) this digital input can control the high sides and low sides drivers in normal request- and normal mode. to enable pwm control, th e mcu must perform a write operation to the high side cont rol register (hscr) or the low side control register (lscr). this pin has an internal 20 a current pull-up.
analog integrated circuit device data 22 freescale semiconductor 33912 functional description functional pin description reset pin (rst ) this bidirectional pin is used to reset the mcu in case the 33912 detects a reset condition, or to inform the 33912 that the mcu has just been reset. after release of the rst pin, normal request mode is entered. the rst pin is an active low filtered input and output formed by a weak pull-up and a switchable pull-down structure which allows this pi n to be shorted either to v dd or to gnd during software development, without the risk of destroying the driver. interrupt pin (irq ) the irq pin is a digital output used to signal events or faults to the mcu while in normal and normal request mode or to signal a wake-up from st op mode. this active low output will transition to high only after the interrupt is acknowledged by a spi read of the respective status bits. watchdog configuration pin (wdconf) the wdconf pin is the configuration pin for the internal watchdog. a resistor can be connected to this pin to configure the window watchdog period. when connected directly to ground, the watchdog will be disabled. when this pin is left open, the watchdog period is fi xed to its lower precision internal default value (150ms typical). ground connection pins (agnd, pgnd, lgnd) the agnd, pgnd and lgnd pins are the analog and power ground pins. the agnd pin is the ground reference of the voltage regulator and the current sense module. the pgnd and lgnd pins are used for high current load return as in the relay-drivers and lin interface pin. note: pgnd, agnd and lgnd pins must be connected together. current sense amplifier input pins (isenseh and isensel) the isenseh and isensel pins are the input pins of a ground compatible differential amplifier designed to be used to sense the voltage drop over a shunt resistor. the main purpose of this amplifier is to implement accurate current sensors. the gain of the differential amplifier can be set by spi. low side pins (ls1 and ls2) ls1 and ls2 are the low side driver outputs. those outputs are short-circuit protec ted and include active clamp circuitry to drive inductive loads. due to the energy clamp voltage on this pin, it can raise above the battery level when switched off. the s witches are controlled through the spi and can be configured to respond to a signal applied to the pwmin input pin. both low side switches are pr otected against overheating. digital/analog pins (l 1, l2, l3 and l4) the lx pins are multi purpose inputs. they can be used as digital inputs, which can be sampled by reading the spi and used for wake-up when 33912 is in low power mode or used as analog inputs for the analog multiplexer. when used to sense voltage outside the module, a 33kohms series resistor must be used on each input. when used as wake-up inputs l1-l4 can be configured to operate in cyclic-sense mode. in this mode one of the high side switches is configured to be periodically turned on and sample the wake-up inputs. if a state change is detected between two cycles a wake-up is initiated. the 33912 can also wake-up from stop or sleep by a simple state change on l1-l4. when used as analog inputs, t he voltage present on the lx pins is scaled down by an selectable internal voltage divider and can be routed to the adout0 output through the analog multiplexer. note: if an lx input is selected in the analog multiplexer, it will be disabled as a digital input and remains disabled in low power mode. no wake-up feat ure is available in that condition. when an lx input is not selected in the analog multiplexer, the voltage divider is disconnected from that input. high side output pins (hs1 and hs2) these two high side switches ar e able to drive loads such as relays or lamps. their struct ures are connected to the vs2 supply pin. the pins are s hort-circuit protected and both outputs are also protected against overheating. hs1 and hs2 are controlled by spi and can respond to a signal applied to the pwmin input pin. hs1 and hs2 outputs can also be used during low-power mode for the cyclic-sense of the wake inputs. power supply pins (vs1 and vs2) those are the battery level voltage supply pins. in an application, vs1 and vs2 pins must be protected against reverse battery connection and negative transient voltages with external components. th ese pins sustain standard automotive voltage conditions such as a load dump at 40v. the high side switches (hs1 and hs2) are supplied by the vs2 pin. all other internal blocks are supplied by vs1 pin.
analog integrated circuit device data freescale semiconductor 23 33912 functional description functional pin description voltage sense pin (vsense) this input can be connected directly to the battery line. it is protected against battery reverse connection. the voltage present in this input is scaled down by an internal voltage divider, and can be routed to the adout0 output pin and used by the mcu to read the battery voltage. the esd structure on this pin allows for excursion up to +40v and down to -27v, allowing this pin to be connected directly to the battery line. it is strongly recommended to connect a 10kohm resistor in seri es with this pin for protection purposes. hall sensor switchable supply pin (hvdd) this pin provides a switchable supply for external hall sensors. while in normal mode , this current limited output can be controlled through the spi. the hvdd pin needs to be connected to an external capacitor to stabilize the regulated output voltage. +5v main regulator output pin (vdd) an external capacitor has to be placed on the vdd pin to stabilize the regulated output voltage. the vdd pin is intended to supply a microcontro ller. the pin is current limited against shorts to gnd and over-temperature protected. during stop mode, the voltage regulator does not operate with its full drive capabilities and the output current is limited. during sleep mode, the regulator output is completely shut down.
analog integrated circuit device data 24 freescale semiconductor 33912 functional description functional internal block description functional internal block description figure 14. functional internal block diagram analog circuitry the 33912 is designed to operate under automotive operating conditions. a fully configurable window watchdog circuit will reset the connected mcu in case of an overflow. two low power modes are available with several different wake-up sources to reactivate the device. four analog / digital inputs can be sensed or used as the wake-up source. the device is capable of sensing the supply voltage (vsense), the internal chip te mperature (ctemp) as well as the motor current using an external sense resistor. high side drivers two current and temperature protected high side drivers with pwm capability are provided to drive small loads such as status led?s or small lamps. both drivers can be configured for periodic sense during low power modes. low side drivers two current and temperature protected low side drivers with pwm capability are provid ed to drive h-bridge type relays for power motor applications mcu interface the 33912 is providing its co ntrol and status information through a standard 8-bit spi inte rface. critical system events such as low- or high-voltage/temperature conditions as well as over-current conditions in any of the driver stages can be reported to the connected mcu via irq or rst. both low side and both high side driver outputs can be controlled via the spi register as well as the pwmin input. the integrated lin physical layer interface can be configured via spi register and its communication is driven through the rxd and txd device pins. all internal analog sources are multiplexed to the a dout 0 pin. the current sense analog signal is directly routed through adout1. voltage regulator outputs two independent voltage regu lators are implemented on the 33912. the vdd main regulator output is designed to supply a mcu with a precise 5v. the switchable hvdd output is dedicated to supply small peripherals as hall sensors. lin physical layer interface the 33912 provides a lin 2.0 compatible lin physical layer interface with select able slew rate and various diagnostic features. MC33912 - functional block diagram ana l og circuitr y mcu inter f ace and output control d riv e r s i ntegrate d supp ly hi g h s ide drivers h s 1 - h s 2 lin phy s i ca l l a y er int e r face l o w s i de driv e r s l s 1 - l s 2 integrated supply hall sensor supply hvdd voltage regulator vdd a nalo g circuitr y digital / analog input voltage, current & temperature sense wake-up window watchdog mcu interface and output control s pi int e rf ace l s/ h s - pwm co ntr o l analog output 0/1 l in interface / control r eset & ir q lo g ic
analog integrated circuit device data freescale semiconductor 25 33912 functional device operations operational modes functional device operations operational modes int roduction the 33912 offers three main operating modes: normal (run), stop, and sleep (low power). in normal mode, the device is active and is operating under normal application conditions. the stop and sleep modes are low-power modes with wake-up capabilities. in stop mode, the voltage regulator still supplies the mcu with v dd (limited current capability), while in sleep mode the voltage regulator is turned off (v dd = 0 v). wake-up from stop mode is initiated by a wake-up interrupt. wake-up from sleep mode is done by a reset and the voltage regulator is turned back on. the selection of the different modes is controlled by the mod1:2 bits in the mode control register (mcr). figure 15 describes how transitions are done between the different operating modes. table 5 , 27 , gives an overview of the operating modes. reset mode the 33912 enters the reset mode after a power up. in this mode, the rst pin is low for 1ms (typical value). after this delay, it enters the normal request mode and the rst pin is driven high. the reset mode is entered if a reset condition occurs (v dd low, watchdog trigger fail, after wake-up from sleep mode, normal request mode timeout occurs). normal request mode this is a temporary mode automatically accessed by the device after the reset mode, or after a wake-up from stop mode. in normal request mode, the vdd regulator is on, the reset pin is high, and the li n is operating in rx only mode. as soon as the device enters in the normal request mode an internal timer is started for 150ms (typical value). during these 150ms, the mcu must co nfigure the timing control register (timcr) and the mode control register (mcr) with mod2 and mod1 bits set = 0, to enter the normal mode. if within the 150ms timeout, the mcu does not command the 33912 to normal mode, it will enter in reset mode. if the wdconf pin is grounded in order to disable the watchdog function, it goes directly in normal mode after the reset mode. if the wdconf pin is op en, the 33912 stays typically for 150ms in normal request before entering in normal mode. normal mode in normal mode, all 33912 functions are active and can be controlled by the spi interface and the pwmin pin. the vdd regulator is on and delivers its full current capability. if an external resistor is connected between the wdconf pin and the ground, the window watchdog function will be enabled. the wake-up inputs (l1-l4) can be read as digital inputs or have its voltage routed through the analog-multiplexer. the lin interface has slew rate and timing compatible with the lin protocol specification 2.0. the lin bus can transmit and receive information. the high side and low side switches are active and have pwm capability according to the spi configuration. the interrupts are generated to report failures for v sup over/under -voltage, thermal s hutdown, or thermal shutdown prewarning on the main regulator. sleep mode the sleep mode is a low power mode. from normal mode, the device enters into sleep mode by sending one spi command through the mode control register (mcr). all blocks are in their lowest po wer consumption condition. only some wake-up sources (wake-up inputs with or without cyclic sense, forced wake-up and lin receiver) are active. the 5v regulator is off. the internal low-power oscillator may be active if the ic is configured fo r cyclic-sense. in this condition, one of the high side switches is turned on periodically and the wake-up inputs are sampled. wake-up from sleep mode is similar to a power-up. the device goes in reset mode exce pt that the spi will report the wake-up source and the batfail flag is not set. stop mode the stop mode is the second low power mode, but in this case the 5v regulator is on with limited current drive capability. the application mcu is always supplied while the 33912 is operating in stop mode. the device can enter into stop mode only by sending the spi command. when the application is in this mode, it can wake-up from the 33912 side (f or example: cyclic sense, force wake-up, lin bus, wake inputs) or the mcu side (cs , rst pins). wake-up from stop mode will transition the 33912 to normal request mode and generates an interrupt except if the wake-up event is a low to high transition on the cs pin or comes from the rst pin.
analog integrated circuit device data 26 freescale semiconductor 33912 functional device operations operational modes figure 15. operating modes and transitions reset power down notes: wd - means watchdog wd disabled - means watchdog disabled (wdconf terminal connected to gnd) wd trigger ? means watchdog is triggered by spi command wd failed ? means no watchdog trigger or trigger occurs in closed window stop command - means stop command sent via spi sleep command - means sleep command send via spi wake-up - means l1 or l2 state change or lin bus wake up or ss rising edge normal request v dd high and reset delay (t rst ) expired normal normal request timeout expired (nr tout ) wd trigger sleep wake-up (reset) stop v dd low v dd low (>nr tout ) expired and vsuv = 0 sleep command v dd low stop command wake-up interrupt wd disabled v dd low wd failed normal request time-out expired (t nrtout ) v dd high and reset delay (t rst ) expired v dd low v dd low wd failed v dd low (>t nrtout ) expired and vsuv = 0 sleep command stop command wake-up (reset) wd trigger wd disabled power up wake-up (interrupt) legend wd: watchdog wd disabled: watchdog disabled (w dconf pin connected to gnd) wd trigger: watchdog is triggered by spi command wd failed: no watchdog trigger or trigger occurs in closed window stop command: stop command sent via spi sleep command: sleep command sent via spi wake-up from stop mode: l1, l2, l3 or l4 state change, lin bus wake-up, periodic wake-up, c s rising edge wake-up or rst wake-up. v dd low wake-up from sleep mode: l1, l2, l3 or l4 state change, lin bus wake-up, periodic wake-up.
analog integrated circuit device data freescale semiconductor 27 33912 functional device operations operational modes interrupts interrupts are used to signal a microcontroller that a peripheral needs to be serviced. the interrupts which can be generated, change according to the operating mode. while in normal and normal request modes, the 33912 signals through interrupts special conditions which may require a mcu software action. interr upts are not generated until all pending wake-up sources are read in the interrupt source register (isr). while in stop mode, interrupts are used to signal wake-up events. sleep mode does not use interrupts. wake-up is performed by powering-up the mcu. in normal and normal request mode the wake-up source can be read by spi. the interrupts are signaled to the mcu by a low logic level of the irq pin, which will remain low until the interrupt is acknowledged by a spi read. the irq pin will then be driven high. interrupts are only asserted while in normal, normal request and stop mode. interrupts are not generated while the rst pin is low. the following is a list of the interrupt sources in normal and normal request modes. some of these can be masked by writing to the spi - interrupt mask register (imr). low-voltage interrupt: signals when the supply line (vs1) voltage drops below the vsuv threshold ( v suv ). high-voltage interrupt: signals when the supply line (vs1) voltage increases above the vsov threshold ( v sov ). over-temperature prewarning: signals when the 33912 temp erature has reached the pre- shutdown warning threshold. it is used to warn the mcu that an over-temperature shutdown in the main 5v regulator is imminent. lin over-current shutdown / over-temperature shutdown / txd stuck at dominant / rxd short-circuit: these signal fault conditions within the lin interface will cause the lin driver to be disa bled, except for the lin over- current condition. in order to re start operation, the fault must be removed and must be acknowledged by reading the spi. the linoc bit functionality in the lin status register (linsr) is to indicate an lin over-current has occurred and the driver remains enabled. high side over-temperature shutdown: signals a shutdown in the high side outputs. low side over-temperature shutdown: signals a shutdown in the low side outputs. reset to reset a mcu the 33912 drives the rst pin low for the time the reset condition lasts. table 5. operating modes overview function reset mode normal request mode normal mode stop mode sleep mode vdd full full full stop - hvdd - spi (55) spi - - lsx - spi/pwm (56) spi/pwm - - hsx - spi/pwm (56) spi/pwm note (57) note (58) analog mux - spi spi - - lx - inputs inputs wake-up wake-up current sense on on on - - lin - rx-only full/rx-only rx-only/wake-up wake-up watchdog - 150ms (typ.) timeout on (59) /off - - vsense on on on vdd - notes 55. operation can be enabled/controlled by the spi. 56. operation can be controlled by the pwmin input. 57. hsx switches can be configured for cyclic sense operation in stop mode. 58. hsx switches can be configured fo r cyclic sense operation in sleep mode. 59. windowing operation when enabled by an external resistor.
analog integrated circuit device data 28 freescale semiconductor 33912 functional device operations operational modes after the reset source is re moved, the state machine will drive the rst output low for at least 1ms (typical value) before driving it high. in the 33912, four main reset sources exist: 5v regulator low-voltage-reset (v rst th ) the 5v regulator output v dd is continuously monitored against brown outs. if the supp ly monitor detects that the voltage at the vdd pin has dropped below the reset threshold v rst th the 33912 will issue a reset. in case of over- temperature, the voltage regulator will be disabled and the voltage monitoring will issue a vddot flag independently of the v dd voltage. window watchdog overflow if the watchdog counter is not properly serviced while its window is open, the 33912 will detect an mcu software run- away and will reset the microcontroller. wake-up from sleep mode during sleep mode, the 5v regulator is not active, hence all wake-up requests from sleep mode require a power-up/ reset sequence. external reset the 33912 has a bidirectional reset pin which drives the device to a safe state (same as reset mode) for as long as this pin is held low. the r st pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. this functionality is also active in stop mode. after the rst pin is released, there is no extra t rst to be considered. wake-up capabilities once entered into one of the low-power modes (sleep or stop) only wake-up sources can bring the device into normal mode operation. in stop mode, a wake-up is signaled to the mcu as an interrupt, while in sleep mode the wake-up is performed by activating the 5v regulator and resetting the mcu. in both cases the mcu can detect the wake-up source by accessing the spi registers. there is no spec ific spi register bit to signal a cs wake-up or external reset. if necessary this condition is detected by excluding all other possible wake-up sources. wake-up from wake-up inputs (l1-l4) with cyclic sense disabled the wake-up lines are dedicated to sense state changes of external switches and wake -up the mcu (in sleep or stop mode). in order to select and activate direct wake-up from lx inputs, the wake-up control register (wucr) must be configured with appropriate lxwe inputs enabled or disabled. the wake-up input?s state is read through the wake-up status register (wusr). lx inputs are also used to perform cyclic-sense wake-up. note: selecting an lx input in the analog multiplexer before entering low power mode will disable the wake-up capability of the lx input wake-up from wake-up inputs (l1-l4) with cyclic sense timer enabled the sbclin can wake-up at the end of a cyclic sense period if on one of the four wake -up input lines (l1-l4) a state change occurs. the hsx switch is activated in sleep or stop modes from an internal timer. cyclic sense and force wake- up are exclusive. if cyclic se nse is enabled, the force wake- up can not be enabled. in order to select and activate the cyclic sense wake-up from lx inputs, before entering in low power modes (stop or sleep modes), the following spi set-up has to be performed: in wucr: select the lx input to wu-enable. in hscr: enable the desired hsx. ? in timcr: select the cs/ wd bit and determine the cyclic sense period with cystx bits. ? perform goto sleep/stop command. forced wake-up the 33912 can wake-up automatically after a predetermined time spent in sleep or stop mode. cyclic sense and forced wake-up are exclusive. if forced wake-up is enabled, the cyclic sense can not be enabled. to determine the wake-up peri od, the following spi set-up has to be sent before entering in low power modes: ? in timcr: select the cs/ wd bit and determine the low power mode period with cystx bits. ? in hscr: all hsx bits must be disabled. cs wake-up while in stop mode, a rising edge on the cs will cause a wake-up. the c s wake-up does not generate an interrupt, and is not reported on spi. lin wake-up while in the low-power mode, the 33912 monitors the activity on the lin bus. a dominant pulse larger than t propwl followed by a dominant to recessive transition will cause a lin wake-up. this behavior prot ects the system from a short to ground bus condition.
analog integrated circuit device data freescale semiconductor 29 33912 functional device operations operational modes rst wake-up while in stop mode, the 33912 can wake-up when the rst pin is held low long enough to pass the internal glitch filter. then, the 33912 will change to normal request or normal modes depending on the wdconf pin configuration. the r st wake-up does not generate an interrupt and is no t reported via spi. from stop mode, the following wake-up events can be configured: ? wake-up from lx inputs without cyclic sense ? cyclic sense wake-up inputs ? force wake-up ? cs wake-up ? lin wake-up ? rst wake-up from sleep mode, the following wake-up events can be configured: ? wake-up from lx inputs without cyclic sense ? cyclic sense wake-up inputs ? force wake-up ? lin wake-up window watchdog the 33912 includes a configurable window watchdog which is active in normal mode. the watchdog can be configured by an external resistor connected to the wdconf pin. the resistor is used to achieve higher precision in the timebase used for the watchdog. spi clears are performed by writing through the spi in the mod bits of the mode control register (mcr). during the first half of the spi timeout, watchdog clears are not allowed, but after the first half of the spi timeout window, the clear operation opens. if a clear operation is performed outside the window, the 33912 will reset the mcu, in the same way as when the watchdog overflows. figure 16. window watchdog operation to disable the watchdog function in normal mode the user must connect the wdconf pin to ground. this measure effectively disables normal request mode. the wdoff bit in the watchdog status register (wdsr) will be set. this condition is only detected during reset mode. if neither a resistor nor a co nnection to ground is detected, the watchdog falls back to the internal lower precision timebase of 150ms (typ.) and signals the faulty condition through the watchdog status register (wdsr). the watchdog timebase can be further divided by a prescaler which can be configured by the timing control register (timcr). during normal request mode, the window watchdog is not active but there is a 150ms (typ.) timeout for leaving the normal request mode. in case of a timeout, the 33912 will enter into reset mode, resetting the microcontroller before entering again into normal request mode. high side output pins hs1 and hs2 these outputs are two high side drivers intended to drive small resistive loads or leds incorporating the following features: ? pwm capability (software maskable) ? open load detection ? current limitation ? over-temperature shutdown (with maskable interrupt) ? high-voltage shutdown (software maskable) ? cyclic sense the high side switches are controlled by the bits hs1:2 in the high side control register (hscr). pwm capability (direct access) each high side driver offers additional (to the spi control) direct control via the pwmin pin. if both the bits hs1 and pwmhs1 are set in the high side control register (hscr), then the hs1 driver is turned on if the pwmin pin is high and turned of if the pwmin pin is low. this applies to hs2 configuring hs2 and pwmhs2 bits. wd period (t pwd ) window closed no watchdog clear allowed window open for watchdog clear wd timing x 50% wd timing x 50% wd timing selected by register on wdconf pin
analog integrated circuit device data 30 freescale semiconductor 33912 functional device operations operational modes figure 17. high side drivers hs1 and hs2 open load detection each high side driver signals an open load condition if the current through the high side is below the open load current threshold. the open load condition is indi cated with the bits hs1op and hs2op in the high side status register (hssr). current limitation each high side driver has an output current limitation. in combination with the over-tem perature shutdown the high- side drivers are protected against over-current and short- circuit failures. when the driver operates in th e current limitation area, it is indicated with the bits hs1cl and hs2cl in the hssr. note: if the driver is operatin g in current limitation mode, excessive power might be dissipated. over-temperature protection (hs interrupt) both high side drivers are protected against over- temperature. in case of an ov er-temperature condition both high side drivers are shut down and the event is latched in the interrupt control module. the shutdown is indicated as hs interrupt in the interrupt source register (isr). a thermal shutdown of the high side drivers is indicated by setting all hsxop and hsxcl bits simultaneously. if the bit hsm is set in the interrupt mask r egister (imr), then an interrupt (irq ) is generated. a write to the high side control register (hscr), when the over-temperature conditio n is gone, will re-enable the high side drivers. high-voltage shutdown in case of a high voltage condition and if the high voltage shutdown is enabled (bit hvse in the mode control register (mcr) is set) both high si de drivers are shut down. a write to the high side control register (hscr), when the high voltage condition is go ne, will re-enable the high side drivers. sleep and stop mode the high side drivers can be enabled to operate in sleep and stop mode for cyclic sensing. also see table 5, operating modes overview . high side - driver charge pump open load detection current limitation overtemperture shutdown (interrupt maskable) high voltage shutdown (maskable) control on/off status pwmin v dd pwmhsx hsx hvse hsxop hsxcl mod1:2 interrupt control module hsx vs2 high voltage shutdown high-side interrupt v dd wakeup module cyclic sense
analog integrated circuit device data freescale semiconductor 31 33912 functional device operations operational modes low side output pins ls1 and ls2 these outputs are two low side drivers intended to drive relays incorporating the following features: ? pwm capability (software maskable) ? open load detection ? current limitation ? over-temperature shutdown (with maskable interrupt) ? active clamp (for driving relays) ? high-voltage shutdown (software maskable) the low side switches are contro lled by the bit ls1:2 in the low side control register (lscr). to protect the device agai nst over-voltage when an inductive load (relay) is turned off. an active clamp will re- enable the low side fet if the voltage on the ls1 or ls2 pin exceeds a certain level. pwm capability (direct access) each low side driver offers additional (to the spi control) direct control via the pwmin pin. if both the bits ls1 and pwmls1 are set in the low side control register (lscr), then the ls1 driver is turned on if the pwmin pin is high and turned off if the pwmin pin is low. the same applies to the ls2 and pwmls2 bits for the ls2 driver. figure 18. low side drivers ls1 and ls2 open load detection each low side driver signals an open load condition if the current through the low side is below the open load current threshold. the open load condition is in dicated with the bit ls1op and ls2op in the low side status register (lssr). current limitation each low side driver has a current limitation. in combination with the over-tem perature shutdown the low side drivers are protected against over-current and short- circuit failures. when the drivers operate in current limitation, this is indicated with the bits ls1cl and ls2cl in the lssr. note: if the drivers are operat ing in current limitation mode excessive power might be dissipated. over-temperature protec tion (ls interrupt) both low side drivers are protected against over- temperature. in case of an ov er-temperature condition both low side drivers are shut down and the event is latched in the interrupt control module. the s hutdown is indicated as an ls interrupt in the interrupt source register (isr). if the bit lsm is set in the interrupt mask register (imr) than an interrupt (irq ) is generated. a write to the low side control register (lscr), when the over-temperature condition is gone, will re-enable the low side drivers. high-voltage shutdown in case of a high-voltage condition and if the high-voltage shutdown is enabed (bit hvse in the mode control register (mcr) is set) both low sides drivers are shut down. a write to the low side control register (lscr), when the high-voltage condition is gone, will re-enable the low side drivers. sleep and stop mode the low side drivers are disabled in sleep and stop mode. also see table 5, operating modes overview . lsx low side driver (active clamp) open-load detection current limitation over-temperture shutdown (interrupt maskable) high-voltage shutdown (maskable) pgnd active clamp interrupt control module hvse control on/off status lsx lsxop lsxcl mod1:2 high-voltage shutdown low side interrupt pwmin v dd pwmlsx v dd
analog integrated circuit device data 32 freescale semiconductor 33912 functional device operations operational modes lin physical layer the lin bus pin provides a physical layer for single-wire communication in automotive applications. the lin physical layer is designed to meet the lin physical layer specification and has the following features: ? lin physical la yer 2.0 compliant ? slew rate selection ? over-current shutdown ? over-temperature shutdown ? lin pull-up disable in stop and sleep modes ? advanced diagnostics ? lin dominant voltage level selection the lin driver is a low side mosfet with over-current and thermal shutdown. an internal pull-up resistor with a serial diode structure is integrated, so no external pull-up components are required for the application in a slave node. the fall time from dominant to recessive and the rise time from recessive to dominant is controlled. the symmetry between both slopes is guaranteed. lin pin the lin pin offers a high susceptibility immunity level from external disturbance, guar anteeing communication during external disturbance. figure 19. lin interface slew rate selection the slew rate can be selected for optimized operation at 10.4 and 20kbit/s as well as a fast baud rate for test and programming. the slew rate can be adapted with the bits lsr1:0 in the lin control regi ster (lincr). the initial slew rate is optimized for 20kbit/s. lin pull-up disable in stop and sleep modes in cases of a lin bus short to gnd or lin bus leakage during low-power mode, the internal pull-up resistor on the lin pin can be disconnected by clearing the linpe bit in the mode control register (mcr). the linpe bit also changes the bus wake-up threshold ( v buswu ). this feature will r educe the current consumption in stop and sleep modes. it also improves performance and safe operation. high-voltage high side rxonly mod1:2 lsr0:1 linpe ldvs interrupt control module lin ? driver slope and slew rate control over-current shutdown (interrupt maskable) over-temperature shutdown (interrupt maskable) vs1 wake-up rxshort linoc txdom linot lin filter slope control 30k lgnd lin receiver txd rxd interrupt shutdown wake-up wake-up module
analog integrated circuit device data freescale semiconductor 33 33912 functional device operations operational modes current limit (lin interrupt) the output low side fet is pr otected against over-current conditions. in case of an ove r-current condition (e.g. lin bus short to v bat ), the transmitter will not be shut down. the bit linoc in the lin status register (linsr) is set. if the linm bit is set in the interrupt mask register (imr), an interrupt irq will be generated. over-temperature shutdo wn (lin interrupt) the output low side fet is protected against over- temperature conditions. in ca se of an over-temperature condition, the transmitter will be shut down and the linot bit in the lin status register (linsr) is set. if the linm bit is set in the interrupt mask register (imr), an interrupt irq will be generated. the transmitter is automatically re-enabled once the condition is gone and txd is high. a read of the lin status register (linsr) with the txd pin high, will re-enable the transmitter. rxd short-circuit dete ction (lin interrupt) the lin transceiver has a short-circuit detection for the rxd output pin. in case of an s hort-circuit condition, either 5v or ground, the rxshort bit in the lin status register (linsr) is set and the transmitter is shut down. if the linm bit is set in the interrupt mask register (imr), an interrupt irq will be generated. the transmitter is automatically re-enabled once the condition is gone (transition on rxd) and txd is high. a read of the lin status regi ster (linsr) without the rxd pin short-circuit condition will clear the bit rxshort. txd dominant detection (lin interrupt) the lin transceiver monitors the txd input pin to detect a stuck in dominant (0v) condition. in case of a stuck condition (txd pin 0v for more than 1 second (typ.)), the transmitter is shut down and the txdom bit in the lin status register (linsr) is set. if the linm bit is set in the imr, an interrupt irq will be generated. the transmitter is automatical ly re-enabled once txd is high. a read of the lin status register (linsr) with the txd pin at 5v will clear the bit txdom. lin dominant voltage level selection the lin dominant voltage leve l can be selected by the bit ldvs in the lin control register (lincr). lin receiver operation only while in normal mode, the activation of the rxonly bit disables the lin txd driver. if case of a lin error condition, this bit is automatica lly set. if a low-power mode is selected with this bit set, the lin wake -up functionality is disabled, then in stop mode, the rxd pin will reflect the state of the lin bus. stop mode and wake-up feature during stop mode operation, the transmitter of the physical layer is disabled. if t he lin-pu bit was set in the stop mode sequence, the internal pull-up resistor is disconnected from vsup and a small current source keeps the lin pin in the recessive state. the receiver is still active and able to detect wake-up events on the lin bus line. a dominant level longer than t propwl followed by a rising edge will generate a wake-up interrupt, and will be reported in the interrupt source register (isr). also see figure 11 , page 19 . sleep mode and wake-up feature during sleep mode operation, the transmitter of the physical layer is disabled. if the lin-pu bit was set in the sleep mode sequence, the internal pull-up resistor is disconnected from v sup and a small current source keeps the lin pin in recessive state. t he receiver must be active to detect wake-up events on the lin bus line. a dominant level longer than t propwl followed by a rising edge will generate a system wake-up (reset), and will be reported in the interrupt source register (isr). also see figure 10 , page 19 .
analog integrated circuit device data 34 freescale semiconductor 33912 functional device operations logic commands and registers logic commands and registers 33912 spi interface and configuration the serial periphera l interface creates the communication link between a microcontroller (master) and the 33912. the interface consists of four pins (see figure 20 ): ? cs ? chip select ?mosi ? master-out slave-in ?miso ? master-in slave-out ?sclk? serial clock a complete data transfer via the spi consists of 1 byte. the master sends 4 bits of addre ss (a3:a0) + 4 bits of control information (c3:c0) and the slave replies with 4 system status bits (vms,lins,hss, lss) + 4 bits of status information (s3:s0). figure 20. spi protocol during the inactive phase of the cs (high), the new data transfer is prepared. the falling edge of the cs indicates the start of a new data transfer and puts the miso in the low-impedance state and latches the analog status da ta (register read data). with the rising edge of the spi clock (sclk), the data is moved to miso/mosi pins. with the falling edge of the spi clock (sclk), the data is sampled by the receiver. the data transfer is only valid if exactly 8 sample clock edges are present during the active (low) phase of cs . the rising edge of the chip select cs indicates the end of the transfer and latches t he write data (mosi) into the register. the cs high forces miso to the high impedance state. register reset values are described along with the reset condition. reset condition is the condition causing the bit to be set to its reset value. th e main reset conditions are: - power-on reset (por): the level at which the logic is reset and batfail flag sets. - reset mode - reset done by the rst pin (ext_reset) cs mosi miso sclk a2 a1 a0 c3 c2 c1 c0 a3 vms lins hss lss s3 s2 s1 s0 read data latch rising edge of sclk change miso/miso output falling edge of sclk sample miso/miso input write data latch register write data register read data
analog integrated circuit device data freescale semiconductor 35 33912 functional device operations logic commands and registers spi register overview table 7 summarizes the spi register content for control info rmation (c3:c0)=w and status information (s3:s0) = r. table 6. system status register adress(a3:a0) register name / read / write information bit 7654 $0 - $f syssr - system status register r vms lins hss lss table 7. spi register overview adress(a3:a0) register name / read / write information bit 3 2 1 0 $0 mcr - mode control register w hvse linpe mod2 mod1 vsr - voltage status register r vsov vsuv vddot batfail $1 vsr - voltage status register r vsov vsuv vddot batfail $2 wucr - wake-up control register w l4we l3we l2we l1we wusr - wake-up status register r l4 l3 l2 l1 $3 wusr - wake-up status register r l4 l3 l2 l1 $4 lincr - lin control register w ldvs rxonly lsr1 lsr0 linsr - lin status register r rxshort txdom linot linoc $5 linsr - lin status register r rxshort txdom linot linoc $6 hscr - high side control register w pwmhs2 pwmhs1 hs2 hs1 hssr - high side status register r hs2op hs2cl hs1op hs1cl $7 hssr - high side status register r hs2op hs2cl hs1op hs1cl $8 lscr - low side control register w pwmls2 pwmls1 ls2 ls1 lssr - low side status register r ls2op ls2cl ls1op ls1cl $9 lssr - low side status register r ls2op ls2cl ls1op ls1cl $a timcr - timing control register w cs/wd wd2 wd1 wd0 cyst2 cyst1 cyst0 wdsr - watchdog status register r wdto wderr wdoff wdwo $b wdsr - watchdog status register r wdto wderr wdoff wdwo $c amuxcr - analog multiplexer control register w lxds mx2 mx1 mx0 $d cfr - configuration register w hvdd cysx8 csaz csgs $e imr - interrupt mask register w hsm lsm linm vmm isr - interrupt source register r isr3 isr2 isr1 isr0 $f isr - interrupt source register r isr3 isr2 isr1 isr0
analog integrated circuit device data 36 freescale semiconductor 33912 functional device operations logic commands and registers register definitions system status register - syssr the system status register (syssr) is always transferred with every spi transmission and gives a quick system status overview. it su mmarizes the status of the voltage status register (vsr), lin status register (linsr), high side status register (hssr ), and the low side status register (lssr). vms - voltage monitor status this read-only bit indicates that one or more bits in the vsr are set. 1 = voltage monitor bit set 0 = none figure 21. voltage monitor status lins - lin status this read-only bit indicates that one or more bits in the linsr are set. 1 = lin status bit set 0 = none figure 22. lin status hss - high side switch status this read-only bit indicates that one or more bits in the hssr are set. 1 = high side status bit set 0 = none figure 23. high side status lss - low side switch status this read-only bit indicates that one or more bits in the lssr are set. 1 = low side status bit set 0 = none figure 24. low side status mode control register - mcr the mode control register (mcr) allows switching between the operation modes and to configure the 33912. writing the mcr will return the vsr. hvse - high-voltage shutdown enable this write-only bit enables/dis ables automatic shutdown of the high side and the low side drivers during a high-voltage vsov condition. 1 = automatic shutdown enabled 0 = automatic shutdown disabled linpe - lin pull-up enable. this write-only bit enables/disables the 30 k ? lin pull-up resistor in stop and sleep mo des. this bit also controls the lin bus wake-up threshold. 1 = lin pull-up resistor enabled 0 = lin pull-up resistor disabled table 8. system status register s7 s6 s5 s4 read vms lins hss lss vms batfail vddot vsuv vsov lins linoc linot txdom rxshort table 9. mode control register - $0 c3 c2 c1 c0 write hvse linpe mod2 mod1 reset value 11-- reset condition por por - - hs2op hs2cl hs1op hs1cl hss ls2op ls2cl ls1op ls1cl lss
analog integrated circuit device data freescale semiconductor 37 33912 functional device operations logic commands and registers mod2, mod1 - mo de control bits these write-only bits select the operating mode and allow clearing the watchdog in accordance with table 10 mode control bits. table 10. mode control bits voltage status register - vsr returns the status of the several voltage monitors. this register is also returned when writing to the mode control register (mcr). vsov - v sup over-voltage this read-only bit indicates an over-voltage condition on the vs1 pin. 1 = over-voltage condition. 0 = normal condition. vsuv - v sup under-voltage this read-only bit indicates an under-voltage condition on the vs1 pin. 1 = under-voltage condition. 0 = normal condition. vddot - main voltage re gulator over-temperature warning this read-only bit indicates that the main voltage regulator temperature reached the ov er-temperature prewarning threshold. 1 = over-temperature prewarning 0 = normal batfail - battery fail flag. this read-only bit is set during power-up and indicates that the 33912 had a power-on-reset (por). any access to the mcr or vsr will clear the batfail flag. 1 = por reset has occurred 0 = por reset has not occurred wake-up control register - wucr this register is used to cont rol the digital wake-up inputs. writing the wucr will return th e wake-up status register (wusr). table 12. wake-up control register - $2 lxwe - wake-up input x enable this write-only bit enables/disables which lx inputs are enabled. in stop and sleep mode the lxwe bit determines which wake inputs are active fo r wake-up. if one of the lx inputs is selected on the analog multiplexer, the corresponding lxwe is masked to 0. 1 = wake-up input x enabled. 0 = wake-up input x disabled. wake-up status register - wusr this register is used to monitor the digital wake-up inputs and is also returned when writing to the wucr. lx - wake-up input x this read-only bit indicates the status of the corresponding lx input. if the lx input is not enabled, then the according wake-up status will return 0. after a wake-up from stop or sleep mode these bits also allow to determine which input has caused the wake-up, by first reading the interrupt st atus register (isr) and then reading the wusr. 1 = lx wake-up. 0 = lx wake-up disabled or selected as analog input. mod2 mod1 description 0 0 normal mode 0 1 stop mode 1 0 sleep mode 1 1 normal mode + watchdog clear table 11. voltage status register - $0/$1 s3 s2 s1 s0 read vsov vsuv vddot batfail c3 c2 c1 c0 write l4we l3we l2we l1we reset value 1111 reset condition por, reset mode or ext_reset table 13. wake-up st atus register - $2/$3 s3 s2 s1 s0 read l4 l3 l2 l1
analog integrated circuit device data 38 freescale semiconductor 33912 functional device operations logic commands and registers lin control register - lincr this register controls the lin physical interface block. writing the lin control register (lincr) returns the lin status register (linsr). * lin failure gone: if lin failure (overtemp, txd/rxd short) was set, the flag resets automatically when the failure is gone. ldvs - lin dominant voltage select this write-only bit controls the lin dominant voltage: 1 = lin dominant voltage = v lin_dom_1 (1.7v typ) 0 = lin dominant voltage = v lin_dom_0 (1.1v typ) rxonly - lin receiver operation only this write-only bit controls the behavior of the lin transmitter. in normal mode, the activation of the rxonly bit disables the lin transmitter. in case of a lin error condition, this bit is automatically set. in stop mode this bit disables the lin wake-up functionality, and the rxd pin will reflect the state of the lin bus. 1 = only lin receiver active (normal mode) or lin wake- up disabled (stop mode). 0 = lin fully enabled. lsrx - lin slew-rate this write-only bit controls the lin driver slew-rate in accordance with table 15 . table 15. lin slew-rate control lin status register - linsr this register returns the status of the lin physical interface block and is also returned when writing to the lincr. rxshort - rxd pin short-circuit this read-only bit indicates a short-circuit condition on the rxd pin (shorted either to 5.0v or to ground). the short- circuit delay must be a worst case of 8s to be detected and to shut down the driver. to clear this bit, it must be read after the condition is gone (transit ion detected on rxd pin). the lin driver is automatically re -enabled once the condition is gone. 1 = rxd short-circuit condition. 0 = none. txdom - txd permanent dominant this read-only bit signals the detection of a txd pin stuck at dominant (ground) condition and the resultant shutdown in the lin transmitter. this cond ition is detected after the txd pin remains in dominant state fo r more than 1 second (typical value). to clear this bit, it must be read after txd has gone high. the lin driver is automatically re-enabled once txd goes high. 1 = txd stuck at dominant fault detected. 0 = none. linot - lin driver o ver-temperature shutdown this read-only bit signals that the lin transceiver was shutdown due to over-temperature. the transmitter is automatically re-enabled after the over-temperature condition is gone and txd is high. the linot bit is cleared after spi read once the condition is gone. 1 = lin over-temperature shutdown 0 = none linoc - lin driver over-current shutdown this read-only bit signals an over-current condition occurred on the lin pin. the lin driver is not shut down but an irq is generated. to clear this bi t, it must be read after the condition is gone. 1 = lin over-current shutdown 0 = none table 14. lin control register - $4 c3 c2 c1 c0 write ldvs rxonly lsr1 lsr0 reset value 0000 reset condition por, reset mode or ext_reset por, reset mode, ext_reset or lin failure gone* por lsr1 lsr0 description 0 0 normal slew rate (up to 20kb/s) 0 1 slow slew rate (up to 10kb/s) 1 0 fast slew rate (up to 100kb/s) 1 1 reserved table 16. lin status register - $4/$5 s3 s2 s1 s0 read rxshort txdom linot linoc
analog integrated circuit device data freescale semiconductor 39 33912 functional device operations logic commands and registers high side control register - hscr this register controls the opera tion of the high side drivers. writing to this register return s the high side status register (hssr). pwmhsx - pwm input control enable. this write-only bit enables/disables the pwmin input pin to control the respective high side switch. the corresponding high side switch must be enabled (hsx bit). 1 = pwmin input controls hsx output. 0 = hsx is controlled only by spi. hsx - hsx switch control. this write-only bit enables/disables the corresponding high side switch. 1 = hsx switch on. 0 = hsx switch off. high side status register - hssr this register returns the stat us of the high side switches and is also returned when writing to the hscr. high side thermal shutdown a thermal shutdown of the high side drivers is indicated by setting all hsxop and hsxcl bits simultaneously. hsxop - high side switch open-load detection this read-only bit signals that the high side switches are conducting current below a certain threshold indicating possible load disconnection. 1 = hsx open load detected (or thermal shutdown) 0 = normal hsxcl - high side current limitation this read-only bit indicates that the respective high side switch is operating in current limitation mode. 1 = hsx in current limitation (or thermal shutdown) 0 = normal low side control register - lscr this register controls the oper ation of the low side drivers. writing the low side control register (lscr) will also return the low side status register (lssr). pwmlx - pwm input control enable. this write-only bit enables/d isables the pwmin input pin to control the respective low side switch. the corresponding low side switch must be enabled (lsx bit). 1 = pwmin input controls lsx. 0 = lsx is controlled only by spi. lsx - lsx switch control. this write-only bit enables/disables the corresponding low side switch. 1 = lsx switch on. 0 = lsx switch off. low side status register - lssr this register returns the stat us of the low side switches and is also returned when writing to the lscr. low side thermal shutdown a thermal shutdown of the low side drivers is indicated by setting all lsxop and lsxcl bits simultaneously. lsxop - low side switch open-load detection this read-only bit signals that the low side switches are conducting current below a certain threshold indicating possible load disconnection. 1 = lsx open load detected (or thermal shutdown) 0 = normal lsxcl - low side current limitation this read-only bit indicates that the respective low side switch is operating in current limitation mode. 1 = lsx in current limitation (or thermal shutdown) 0 = normal table 17. high side control register - $6 c3 c2 c1 c0 write pwmhs2 pwmhs1 hs2 hs1 reset value 00 0 0 reset condition por por, reset mode, ext_reset, hsx over-temp or (vsov & hvse) table 18. high side status register - $6/$7 s3 s2 s1 s0 read hs2op hs2cl hs1op hs1cl table 19. low side control register - $8 c3 c2 c1 c0 write pwmls2 pwmls1 ls2 ls1 reset value 00 0 0 reset condition por por, reset mode, ext_reset, lsx over-temp or (vsov & hvse) table 20. low side status register - $8/$9 c3 c2 c1 c0 read ls2op ls2cl ls1op ls1cl
analog integrated circuit device data 40 freescale semiconductor 33912 functional device operations logic commands and registers timing control register - timcr this register is a double purpo se register which allows to configure the watchdog and the cyclic sense periods. writing to the timing control register (timcr) will also return the watchdog status register (wdsr). cs/wd - cyclic sense or watchdog prescaler select this write-only bit selects wh ich prescaler is being written to, the cyclic sense prescaler or the watchdog prescaler. 1 = cyclic sense prescaler selected 0 = watchdog prescaler select wdx - watchdog prescaler this write-only bits selects the divider for the watchdog prescaler and therefore selects the watchdog period in accordance with table 22 . this configuration is valid only if windowing watchdog is active. table 22. watchdog prescaler cystx - cyclic sense period prescaler select this write-only bits selects the interval for the wake-up cyclic sensing together with the bit cysx8 in the configuration register (cfr) (see page 41 ). this option is only active if on e of the high side switches is enabled when entering in stop or sleep mode. otherwise a timed wake-up is performed after the period shown in table 23 . table 23. cyclic sense interval watchdog status register - wdsr this register returns the wa tchdog status information and is also returned when writing to the timcr. wdto - watchdog timeout this read-only bit signals the last reset was caused by either a watchdog timeout or by an attempt to clear the watchdog within the window closed. any access to this register or the timing control register (timcr) will clear the wdto bit. 1 = last reset caused by watchdog timeout 0 = none table 21. timing control register - $a c3 c2 c1 c0 write cs/wd wd2 wd1 wd0 cyst2 cyst1 cyst0 reset value -000 reset condition -por wd2 wd1 wd0 prescaler divider 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 6 1 0 0 8 1 0 1 10 1 1 0 12 1 1 1 14 cysx8 (60) cyst2 cyst1 cyst0 interval x 0 0 0 no cyclic sense 0 0 0 1 20ms 0 0 1 0 40ms 0 0 1 1 60ms 0 1 0 0 80ms 0 1 0 1 100ms 0 1 1 0 120ms 0 1 1 1 140ms 1 0 0 1 160ms 1 0 1 0 320ms 1 0 1 1 480ms 1 1 0 0 640ms 1 1 0 1 800ms 1 1 1 0 960ms 1 1 1 1 1120ms notes 60. bit cysx8 is located in configuration register (cfr) table 24. watchdog status register - $a/$b s3 s2 s1 s0 read wdto wderr wdoff wdwo
analog integrated circuit device data freescale semiconductor 41 33912 functional device operations logic commands and registers wderr - watchdog error this read-only bit signals the detection of a missing watchdog resistor. in this condition the watchdog is using the internal, lower precision timebase. the windowing function is disabled. 1 = wdconf pin resistor missing 0 = wdconf pin resistor not floating wdoff - watchdog off this read-only bit signals that the watchdog pin connected to ground and therefore disabled. in this case watchdog timeouts are disabled and the device automatically enters normal mode out of reset. this might be necessary for software debugging and for programming the flash memory. 1 = watchdog is disabled 0 = watchdog is enabled wdwo - watchdog window open this read-only bit signals when the watchdog window is open for clears. the purpose of this bit is for testing. should be ignored in case wderr is high. 1 = watchdog window open 0 = watchdog window closed analog multiplexer control register - muxcr this register controls the analog multiplexer and selects the divider ration for the lx input divider. lxds - lx analog input divider select this write-only bit selects the resistor divider for the lx analog inputs. voltage is internally clamped to vdd. 0 = lx analog divider: 1 1 = lx analog divider: 3.6 (typ.) mxx - analog multip lexer input select these write-only bits selects which analog input is multiplexed to the adout0 pin according to table 26 . when disabled or when in stop or sleep mode, the output buffer is not powered and the adout0 output is left floating to achieve lower current consumption. table 26. analog multiplexer channel select configuration register - cfr this register controls the hall sensor supply enable/ disable, the cyclic sense timing multiplier, enables/disables the current sense auto-zero function and selects the gain for the current sense amplifier. hvdd - hall sensor supply enable this write-only bit enables/dis ables the state of the hall sensor supply. 1 = hvdd on 0 = hvdd off cysx8 - cyclic se nse timing x 8. this write-only bit influences the cyclic sense period as shown in table 23 . 1 = multiplier enabled 0 = none csaz - current sense au to-zero function enable this write-only bit enables/disables the circuitry to lower the offset voltage of t he current sense amplifier. 1 = auto-zero function enabled 0 = auto-zero function disabled csgs - current sense amplifier gain select this write-only bit selects th e gain of the current sense amplifier. 1 = 14.5 (typ.) 0 = 30 (typ.) table 25. analog multiplexer control register -$c c3 c2 c1 c0 write lxds mx2 mx1 mx0 reset value 1 000 reset condition por por, reset mode or ext_reset mx2 mx1 mx0 meaning 0 0 0 disabled 0 0 1 reserved 0 1 0 die temperature sensor 0 1 1 vsense input 1 0 0 l1 input 1 0 1 l2 input 1 1 0 l3 input 1 1 1 l4 input table 27. configuration register - $d c3 c2 c1 c0 write hvdd cysx8 csaz csgs reset value 0000 reset condition por, reset mode or ext_reset por por por
analog integrated circuit device data 42 freescale semiconductor 33912 functional device operations logic commands and registers interrupt mask register - imr this register allows masking of some of the interrupt sources. the respective flag s within the interrupt source register (isr) will continue to work but will not generate interrupts to the mcu. the 5v regulator over-temperature prewarning interrupt and unde r-voltage (vsuv) interrupts can not be masked and will always cause an interrupt. writing to the imr will return the isr. hsm - high side interrupt mask this write-only bit enables/dis ables interrupts generated in the high side block. 1 = hs interrupts enabled 0 = hs interrupts disabled lsm - low side interrupt mask this write-only bit enables/dis ables interrupts generated in the low side block. 1 = ls interrupts enabled 0 = ls interrupts disabled linm - lin interrupts mask this write-only bit enables/dis ables interrupts generated in the lin block. 1 = lin interrupts enabled 0 = lin interrupts disabled vmm - voltage moni tor interrupt mask this write-only bit enables/dis ables interrupts generated in the voltage monitor block. the only maskable interrupt in the voltage monitor block is the v sup over-voltage interrupt. 1 = interrupts enabled 0 = interrupts disabled interrupt source register - isr this register allows the mcu to determine the source of the last interrupt or wake-up respectively. a read of the register acknowledges the interrupt and leads irq pin to high, in case there are no other pending interrupts. if there are pending interrupts, irq will be driven high for 10s and then be driven low again. this register is also returned when writing to the interrupt mask register (imr). isrx - interrupt source register these read-only bits indicate the interrupt source following table 30 . if no interrupt is pending then all bits are 0. in case more than one interrupt is pending, the interrupt sources are handled sequentially multiplex. table 30. interrupt sources table 28. interrupt mask register - $e c3 c2 c1 c0 write hsm lsm linm vmm reset value 1111 reset condition por table 29. interrupt source register - $e/$f s3 s2 s1 s0 read isr3 isr2 isr1 isr0 interrupt source priority isr3 isr2 isr1 isr0 none maskable maskable 0 0 0 0 no interrupt no interrupt none 0 0 0 1 lx wake-up from stop mode- highest 0 0 1 0 - hs interrupt (over-temperature) 0 0 1 1 - ls interrupt (over-temperature) 0 1 0 0 lin interrupt (rxshort, txdom, lin ot, lin oc) or lin wake-up 0 1 0 1 voltage monitor interrupt (low voltage and vdd over-temperature) voltage monitor interrupt (high voltage) 0 1 1 0 - forced wake-up lowest
analog integrated circuit device data freescale semiconductor 43 33912 typical application logic commands and registers typical application the 33912 can be configured in several applications. the figure below shows the 33912 in the typical slave node application. voltage regulator spi & control reset control module lvr, hvr, htr, wd, window watchdog module lin physical layer vs2 5v output module hs1 ls2 hvdd vsense isensel analog input module digital input module lin rxd adout0 sclk mosi miso txd cs wake up module current sense module interrupt control module lvi, hvi, hti, oci low side control module vbat sense m odule analog multiplexer l4 l3 l2 l1 hs2 ls1 isenseh pgnd wdconf chip temp sense module pwmin high side control module lgnd internal bus mcu rst irq adout1 agnd pgnd vs1 agnd vdd a/d a/d sci spi timer rst vdd irq c4 c3 r7 c2 c1 d1 v r1 r4 analog input analog input r5 c6 lin r2 r3 hall sensor supply hb type relay r6 motor output c5 bat typical component values: c1 = 47f; c2 = c4 = 100nf; c3 = 10f; c5 = 4.7f; c6 = 220pf r1 = 10k ? ; r2 = r3 = 10k ?; r4 = r5 = 33k ?; r6 = 20 ?; r7 = 20k ? -200k ? recommended configuration of the not connected pins (nc): pin 28 = this pin is not internally co nnected and may be used for pcb routing optimization.
analog integrated circuit device data 44 freescale semiconductor 33912 packaging package dimensions packaging package dimensions important for the most current revision of the package, visit www.freescale.com and select documentation, then under available documentation column select packaging information. ac suffix (pb-free) 32-pin lqfp 98ash70029a revision d
analog integrated circuit device data freescale semiconductor 45 33912 important for the most current revision of the pack- age, visit www.freescale.com and select documentation, package dimensions (continued) ac suffix (pb-free) 32-pin lqfp 98ash70029a revision d
analog integrated circuit device data 46 freescale semiconductor 33912 revision history package dimensions (continued) revision history revision date description of changes 1.0 5/2007 ? initial release 2.0 9/2007 ? several textual corrections ? page 11: ?analog output offset ratio? (lxds=1) changed to ?analog output offset? +/-22mv ? page 11: vsense input divider ratio adjusted to 5,0/5,25/5,5 ? page 12: common mode input impedance corrected to 75k ? ? page 13/15: lin physical layer parameters adjus ted to final lin specification release 3.0 9/2007 ? revision number incremented at engineering request. 4.0 2/2008 ? changed functional block diagram on page 24.
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